Motorola MC68VZ328 - Manual (Page 366)

Index-viii MC68VZ328 User’s Manual
ISR register, 9-13
IRQ6/PD[7:0] pin, 2-6
IRQEN bit
PWMC1 register, 15-4
PWMC2 register, 15-8
SPICONT2 register, 13-16
TCTL1 register, 12-7
TCTL2 register, 12-7
IRTEST bit
UMISC1 register, 14-16
UMISC2 register, 14-26
ISR register, 9-12
IVR register, 9-7
K
KB bit
IPR register, 9-18
ISR register, 9-14
KBENx field, 10-20
Keyboard enable field, see KBENx field
Keyboard interrupt request bit, see KB bit
KPUEN register, 10-36
L
LACD/PC7 pin, 2-7
LACDRC register, 8-17
LBLKC register, 8-15
LCD alternate crystal direction output signal, see
LACD/PC7 pin
LCD blink control register, see LBLKC register
LCD blink divisor 6–0 field, see BDx field
LCD bus bandwidth, see LCD controller
LCD clock select field, see LCDCLK SEL field
LCD clock source select bit, see ACDSLT bit
LCD clocking control register, see LBLKC register
LCD contrast signal, see LCONTRAST/PF0 pin
LCD control bit, see LCDON bit
LCD controller
connection to LCD panel, 8-2
cursor formatting, 8-5
DMA bus bandwidth, calculating, 8-8
DMA, using, 8-8
features, 8-1
first line marker, see LFLM/PC4 pin
graphics modes, 8-6
introduction, 8-1
maximum page width and height, 8-5
operation, 8-2
PANEL_OFF procedure, 8-8
self-refresh mode, 8-9
signals
introduction, 2-7
LACD/PC7, 8-3
LCLK/PC6, 8-3
LD[3:0]/PC[3:0], LD[7:4]/PK[7:4], 8-3
LFLM/PC4, 8-3
LLP/PC5, 8-3
system block diagram, 8-2
timing diagrams, 19-13 to 19-31
using with LCD panel when MSB is pixel 0,0, 2-7
LCD cursor control 1 and 0 field, see CCx field
LCD cursor height 4–0 field, see CHx field
LCD cursor vertical Y pixel 8–0 field, see CYPx field
LCD cursor width 4–0 field, see CWx field
LCD cursor width and height register, see LCWCH
register
LCD cursor X position 9–0 field, see CXPx field
LCD cursor X position register, see LCXP register
LCD cursor Y position register, see LCYP register
LCD data bus bits 7–0, see LD[3:0]/PC[3:0],
LD[7:4]/PK[7:4] pins
LCD frame marker polarity bit, see FLMPOL bit
LCD frame period, calculating, 8-19
LCD frame rate control modulation register, absence
of, 8-19
LCD graphic modes, see LCD controller
LCD gray palette mapping register, see LGPMR register
LCD grayscale 13–10 field, see G13–G10 field
LCD grayscale 23–20 field, see G23–G20 field
LCD line pulse polarity bit, see LPPOL bit
LCD line pulse signal, see LLP/PC5 pin
LCD maximum height field, see YMx field
LCD maximum width field, see XMx field
LCD panel
display mapping illustrated, 8-6
grayscale density, adjusting, 8-20
interface timing diagram, 8-4
interface timing, 8-3
PANEL_OFF signal using GPIO pin, 8-8
panels supported, 8-3
polarity signals, changing, 8-3
screen format illustrated, 8-5
using larger screen sizes, 8-4
LCD panel bus width 1–0 field, see PBSIZ1-0 field
LCD panel interface configuration register, see LPICF
register
LCD panning offset register, see LPOSR register
LCD pixel clock divider register, see LPXCD register
LCD pixel polarity bit, see PIXPOL bit
LCD polarity configuration register, see LPOLCF
register
LCD pulse width 7–0 field, see PWx field
LCD refresh rate 9–0 field, see RRAx field
LCD refresh rate adjustment register, see LRRA register
LCD screen height register, see LYMAX register
LCD screen starting address field, see SSAx field
LCD screen starting address register, see LSSA register