Motorola MC68VZ328 - Manual (Page 262)

14-10 MC68VZ328 User’s Manual
Programming Model
14.4 Programming Model
Section 14.4.1, “UART 1 Status/Control Register,” through Section 14.4.14, “FIFO Level Marker
Interrupt Register,” describe the UART registers and detailed information about their settings. The
UART 1 registers are described first.
14.4.1 UART 1 Status/Control Register
The UART 1 status/control register (USTCNT1) controls the overall operation of the UART 1 module.
The bit position assignments for this register are shown in the following register display. The settings for
this register are described in Table 14-4.
USTCNT1 UART 1 Status/Control Register 0x(FF)FFF900
BIT
15
14 13 12 11 10 9 8 7 6 5 4 3 2 1
BIT
0
UEN
RX
EN TX
EN
CL
KM
PE
N
O
DD
ST
OP
8/7
OD
EN
CT
SD RX
FE
RX
HE RX
RE TX
EE TX
HE
TX
AE
TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
RESET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0000
Table 14-4. UART 1 Status/Control Register Description
Name Description Setting
UEN
Bit 15 UART 1 Enable—This bit enables the UART 1 module. This bit
resets to 0.
Note: When the UART 1 module is first enabled after a hard
reset and before the interrupts are enabled, set the UEN and
RXEN bits and perform a word read operation on the URX
register to initialize the FIFO and character status bits.
0 = UART 1 module is disabled
1 = UART 1 module is enabled
RXEN
Bit 14 Receiver Enable—This bit enables the receiver block. This bit
resets to 0. 0 = Receiver is disabled and the
receive FIFO is flushed
1 = Receiver is enabled
TXEN
Bit 13 Transmitter Enable—This bit enables the transmitter block.
This bit resets to 0. 0 = Transmitter is disabled and the
transmit FIFO is flushed
1 = Transmitter is enabled
CLKM
Bit 12 Clock Mode Selection—This bit selects the receiver’s operat-
ing mode. When this bit is low, the receiver is in 16x mode, in
which it synchronizes to the incoming datastream and samples
at the perceived center of each bit period. When this bit is high,
the receiver is in 1x mode, in which it samples the datastream
on each rising edge of the bit clock. In 1x mode, the bit clock is
driven by CLK16. This bit resets to 0. 0 = 16x clock mode (asynchronous
mode)
1 = 1x clock mode (synchronous
mode)
PEN
Bit 11 Parity Enable—This bit controls the parity generator in the
transmitter and the parity checker in the receiver. 0 = Parity is disabled
1 = Parity is enabled
ODD
Bit 10 Odd Parity—This bit controls the sense of the parity generator
and checker. This bit has no function if the PEN bit is low. 0 = Even parity
1 = Odd parity