4 sdram power-down register, Sdram power-down register -18, Table 7-10 – Motorola MC68VZ328 User Manual
Page 128: Sdram power-down register description -18, Sdpwdn sdram power-down register 0x(ff)fffc06
7-18
MC68VZ328 User’s Manual
Programming Model
7.3.4
SDRAM Power-down Register
This register controls how the SDRAM and the MC68VZ328 operate during a power-down operation. The
bit position and values are shown in the following register display. The details about the register settings
are described in Table 7-10.
SDPWDN
SDRAM Power-down Register
0x(FF)FFFC06
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT
0
APEN
PDEN
PDTOUT[3:0]
TYPE
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 7-10. SDRAM Power-down Register Description
Name
Description
Settings
APEN
Bit 15
SDRAM Active Power-down Enable—The bit is set to
make the SDRAM Chip Enable signal go low immediately
when the DRAM controller is not sending a command, writ-
ing data, or reading data with the SDRAM.
0 = APEN disabled.
1 = APEN enabled.
PDEN
Bit 14
SDRAM Precharged Power-down Enable—The bit is set
to make the SDRAM Chip Enable signal go low when the
DRAM controller is not sending a command after the
SDRAM is precharged for a certain time. The time depends
on the value in PDTOUT[3:0].
0 = PDEN disabled.
1 = PDEN enabled.
Reserved
Bits 13–12
Reserved
These bits are reserved and
should be set to 0.
PDTOUT [3:0]
Bits 11–8
SDRAM Precharged Power-down Time Out—The bit is
set to make the SDRAM Chip Enable signal go low when a
time out occurs when the PDEN bit is set. Each binary unit
represents a maximum of 128 clocks. When in power-down
mode, SDRAM can be woken by a CPU or LCD access.
See the description.
Reserved
Bits 7–0
Reserved
These bits are reserved and
should be set to 0.