Motorola MC68VZ328 - Manual (Page 44)

2-2 MC68VZ328 User’s Manual
Signals Grouped by Function
Figure 2-1. Signals Grouped by Function
2.1 Signals Grouped by Function
Table 2-1 on page 2-3 groups the MC68VZ328 signals according to their function.
PM2/DQMH
Processor
Control
Emulation
&
Bootstrap
Memory
Por
t B
VDD
PM1/SDCE
PM3/DQML
PM4/SDA10
PM5/DMOE
PB2/CSC0/RAS0
PB0/CSB0
PB1/CSB1/SDWE
PB3/CSC1/RAS1
PB4/CSD0/CAS0
PB5/CSD1/CAS1
Controller
Chip-Select
16-Bit
Timer
8/16-Bit
PWM
PC[3:0]/LD[3:0]
PC4/LFLM
PC5/LLP
PC6/LCLK
PC7/LACD
PF0/LCONTRAST
PK[7:4]/LD[7:4]
FLX68000
Static
CPU
PE0/SPITXD
PE1/SPIRXD
PE2/SPICLK2
PE3/DWE/UCLK
PE4/RXD1
PE5/TXD1
PE6/RTS1
PE7/CTS1
PJ0/MISO
PJ1/MOSI
PJ2/SPICLK1
PJ3/SS
PJ4/RXD2
PJ5/TXD2
PJ6/RTS2
PJ7/CTS2
PK0/DATA_READY/PWMO2
M/S SPI
with FIFO
16-Bit
Timer
Por
ts C, F
, & K
Por
t E
Por
ts
J &
K
LCD
Controller
Master
SPI
UART with
IRDA1.0
UART
Voltage
Regulator
System
Integration
Module
8/16-Bit
68000
Bus
Interface
Clock
Synthesizer
&
Power
Control
Real-Time
Clock
Interrupt
Controller
Por
t F
PB6/TOUT/TIN
PB7/PWMO1
PF1/IRQ5
PD0/INT0
PD1/INT1
PD2/INT2
PD3/INT3
PD4/IRQ1
PD5/IRQ2
PD6/IRQ3
PD7/IRQ6
PG0/BUSW/DTACK
PG1/A0
LWE/LB
UWE/UB
OE
RESET
PG2/EMUIRQ
PG3/HIZ/P/D
PG4/EMUCS
PG5/EMUBRK
EXTAL
XTAL
Por
t A
PK[2:1]/UDS/LDS/RW
A[19:17]
MA[15:0/A[16:1]
D[15:8]
Por
t D
LVDD
VSS
PM0/SDCLK
CSA0
PF7/CSA1
Por
t G
PF2/CLKO
PF[6:3]/A[23:20]
PA[7:0]/D[7:0]
68000 I
ntern
al
Bu
s
Por
t M