5 chip-select timing trim, 6 dram read cycle 16-bit access (cpu bus master), Chip-select timing trim -8 – Motorola MC68VZ328 User Manual
Page 324: Dram read cycle 16-bit access (cpu bus master) -8, Figure 19-5, Chip-select timing trim timing diagram -8, Table 19-7, Chip-select timing trim timing parameters -8
19-8
MC68VZ328 User’s Manual
AC Electrical Characteristics
19.3.5
Chip-Select Timing Trim
Figure 19-5 shows the timing diagram for the chip-select timing trim. The signal values and units of
measure for this figure are found in Table 19-7. For detailed information about the individual signals, see
Chapter 6, “Chip-Select Logic.”
Figure 19-5. Chip-Select Timing Trim Timing Diagram
19.3.6
DRAM Read Cycle 16-Bit Access (CPU Bus Master)
Figure 19-6 on page 19-9 shows the DRAM read cycle timing diagram for 16-bit access (CPU bus master).
The signal values and units of measure for this figure are found in Table 19-8 on page 19-9. Detailed
information about the operation of individual signals can be found in Chapter 7, “DRAM Controller,” and
Chapter 6, “Chip-Select Logic.”
Table 19-7. Chip-Select Timing Trim Timing Parameters
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
1
CLKO high to CSx asserted (bit ECDS = 0)
—
10
ns
2
CLKO low to CSx asserted (bit ECDS = 1)
—
10
ns
3
UWE/LWE negated before CSx
is negated (bit WPEXT = 0)
10
20
ns
4
UWE/LWE negated before CSx
is negated (bit WPEXT = 1)
40
50
ns
CSx
UWE/LWE
CLKO
S0
S2
S4
WS
S6
S0
CSx
1
UWE/LWE
2
3
4