Motorola MC68VZ328 - Manual (Page 245)

SPI 1 Programming Model
Serial Peripheral Interface 1 and 2 13-9
TEEN
Bit 8 TxFIFO Empty Interrupt Enable—This bit,
when set, causes an interrupt to be generated
when the TxFIFO buffer is empty and the TE bit
is set. 0 = Disable TxFIFO empty interrupt.
1 = Enable TxFIFO empty interrupt.
BO
Bit 7 Bit Count Overflow—This bit is set when the
SPI is in “slave SPI FIFO advanced by SS rising
edge” mode and the slave is receiving more than
16 bits in one burst. This bit is cleared after a
data read from the SPIRXD register.
Note: There is nothing to indicate which data
word has overflowed; hence, the bad data word
may still be in the FIFO if it is not empty.
0 = No bit count overflow.
1 = At least 1 data word in RxFIFO has bit
count overflow error.
RO
Bit 6 RxFIFO Overflow—This bit indicates that the
RxFIFO has overflowed and at least 1 data word
is has been overwritten. The RO flag is automat-
ically cleared after a data read. 0 = RxFIFO has not overflowed.
1 = RxFIFO has overflowed. At least 1 data
word in the RxFIFO is overwritten.
RF
Bit 5 RxFIFO Full Status—This bit, when set, indi-
cates that there are 8 data words in RxFIFO. 0 = Less than 8 data words in RxFIFO.
1 = 8 data words in RxFIFO.
RH
Bit 4 RxFIFO Half Status—This bit, when set, indi-
cates the contents of the RxFIFO is more than or
equal to 4 data words. 0 = Contents of RxFIFO is less than 4 data
words.
1 = Contents of RxFIFO is greater than or
equal to 4 data words.
RR
Bit 3 RxFIFO Data Ready Status—This bit, when
set, indicates that at least 1 data word is ready in
the Rx FIFO. 0 = RxFIFO is empty.
1 = At least 1 data word is ready in the
RxFIFO.
TF
Bit 2 TxFIFO Full Status—This bit, when set, indi-
cates there are 8 data words in the TxFIFO. 0 = Less than 8 data words in TxFIFO.
1 = 8 data words in TxFIFO.
TH
Bit 1 TxFIFO Half Status—This bit, when set, indi-
cates that the contents of the TxFIFO is more
than or equal to 4 data words. 0 = Less than four empty slots in TxFIFO.
1 = More than or equal to four empty slots in
TxFIFO.
TE
Bit 0 TxFIFO Empty Status—This bit, when set,
causes an interrupt to be generated when the
TxFIFO buffer is empty and the TEEN bit is set.
Note: When the FIFO is empty, data shifting
may still be ongoing. To ensure no data
transaction is ongoing, read the XCH bit in
control register.
0 = At least 1 data word is in Tx FIFO.
1 = TxFIFO is empty.
Table 13-4. SPI 1 Interrupt Control/Status Register Description (Continued)
Name Description Setting