Motorola MC68VZ328 - Manual (Page 191)

Programming Model
I/O Ports 10-21
PDIRQEG Port D Interrupt Request Edge Register 0x(FF)FFF41F
10.4.6 Port E Registers
Port E is composed of the following 8-bit general-purpose I/O registers:
• Port E direction register (PEDIR)
• Port E data register (PEDATA)
• Port E pull-up enable register (PEPUEN)
• Port E select register (PESEL)
Each signal in the PEDATA register connects to an external pin. As with the other ports, each bit on Port E
is individually configured. Port E is multiplexed with the serial peripheral interface (SPI) and UART
signals.
10.4.6.1 Port E Direction Register
The Port E direction register controls the direction (input or output) of the line associated with the
PEDATA bit position. When the data bit is assigned to a dedicated I/O function by the PESEL register, the
DIR bits are ignored. The settings for the bit positions of the PEDIR register are shown in Table 10-26.
PEDIR Port E Direction Register 0x(FF)FFF420
BIT 7 6 5 4 3 2 1 BIT 0
IQEG3 IQEG2 IQEG1 IQEG0
TYPE rw rw rw rw
RESET
0 0 0 0 0 0 0 0
0x00
Table 10-25. Port D Interrupt Request Edge Register Description
Name Description Setting
Reserved
Bits 7–4 Reserved These bits are reserved and should be set to 0.
IQEGx
Bits 3–0 Edge Enable—The polarity of the rising or
falling edge is selected by the POLx bits. 0 = Level-sensitive interrupts are selected.
1 = INT[3:0] edge-sensitive interrupts are selected.
BIT 7 6 5 4 3 2 1 BIT 0
DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
TYPE rw rw rw rw rw rw rw rw
RESET
0 0 0 0 0 0 0 0
0x00
Table 10-26. Port E Direction Register Description
Name Description Setting
DIRx
Bits 7–0 Direction—These bits control the direction of the pins in an 8-bit
system. They reset to 0. 0 = Input
1 = Output