Motorola MC68VZ328 - Manual (Page 200)

10-30 MC68VZ328 User’s Manual
Programming Model
BUSW is the default bus width for the CSA0 signal. The DTACK signal is the external input data
acknowledge signal. The MC68VZ328 microprocessor will latch the BUSW signal at the rising edge of the
Reset signal. Its mode will determine the default bus width for CSA0. Bit 1 is Address 0. After system
reset, this signal defaults to A0.
Bit 3 is HIZ/P/D (High Impedance or Program/Data). During system reset, a logic low of this input signal
will put the MC68VZ328 into Hi-Z mode, in which all MC68VZ328 pins are three-stated after reset
release. For normal operation, this pin must be pulled high during system reset or left unconnected. This
pin defaults to a GPIO input pulled high, but can be programmed as the P/D function. P/D is a status signal
used in conjunction with in-circuit emulation that shows whether the current bus cycle is in program space
or in data space during emulation mode. The remaining bits are dedicated in-circuit emulation controls.
See Chapter 16, “In-Circuit Emulation,” for detailed information on their operation.
10.4.8.4 Port G Operational Considerations
Port G can be used as a GPIO as long as caution is exercised. After reset, the Port G pins default to the
dedicated function, except bit 3, which has an I/O function.
To ensure normal operation, the EMUIRQ and
EMUBRK pins must stay high or not be connected during system reset. Otherwise, the chip will enter
emulation mode.
When bits 2–5 are used as I/O, the emulation mode cannot be used during development and debugging.
Once development is complete, bits 2–5 can be used as I/O in the final system. Bit 1 (A0) can be used as
I/O when the system is 16-bit and there is no pull-up after reset for this pin.
10.4.8.5 Port G Pull-up Enable Register
The pull-up enable register (PGPUEN) controls the pull-up resistors for each line in Port G. See
Table 10-39 for the bit settings of the PGPUEN register.
PGPUEN Port G Pull-up Enable Register 0x(FF)FFF432
10.4.8.6 Port G Select Register
The select register (PGSEL) determines if a bit position in the data register (PGDATA) is assigned as a
GPIO or to a dedicated I/O function. See Table 10-40 on page 10-31 for information about setting the bits
in the PGSEL register.
BIT 7 6 5 4 3 2 1 BIT 0
PU5 PU4 PU3 PU2 PU1 PU0
TYPE rw rw rw rw rw rw
RESET
0 0 1 1 1 1 0 1
0x3D
Table 10-39. Port G Pull-up Enable Register Description
Name Description Setting
Reserved
Bits
7–6
Reserved These bits are reserved and should be set to 0.
PUx
Bits 5–0 Pull-up—These bits enable the pull-up
resistors on the port. 0 = Pull-up resistors are disabled
1 = Pull-up resistors are enabled