Motorola MC68VZ328 - Manual (Page 239)

SPI 1 Operation
Serial Peripheral Interface 1 and 2 13-3
13.2.3 SPI 1 Phase and Polarity Configurations
When SPI 1 is used as master, the SPICLK1 signal is used to transfer data in and out of the shift register.
Data is clocked using any one of four programmable clock phase and polarity variations. During phase 0
operation, output data changes on the falling clock edges, and input data is shifted in on rising edges. The
most significant bit is output when the CPU loads the transmitted data. In phase 1 operation, output data
changes on the rising edges of the clock and is shifted in on falling edges. The most significant bit is output
on the first rising SPICLK1 edge. The polarity of SPICLK1 may be configured (to invert the SPICLK1
signal), but it does not change the edge-triggered events that are internal to the SPI 1. This flexibility
allows it to operate with most serial peripheral devices available in the marketplace.
13.2.4 SPI 1 Signals
The following signals are used to control SPI 1:
• MOSI—Master Out/Slave In bidirectional signal, which is multiplexed with PJ0, is the TxD output
signal from the data shift register when in master mode. In slave mode it is the RxD input to the data
shift register.
• MISO—Master In/Slave Out bidirectional signal, which is multiplexed with PJ1, is the RxD input
signal to the data shift register in master mode. In slave mode it is the TxD output from the data shift
register.
• SPICLK1—SPI Clock bidirectional signal, which is multiplexed with PJ2, is the SPI clock output
in master mode. In slave mode it is the input SPI clock signal.
• SS—Slave Select bidirectional signal, which is multiplexed with PJ3, is output in master mode and
input in slave mode.
• DATA_READY—SPI 1 Data Ready input signal is used only in master mode. It is multiplexed with
PK0 and will edge- or level-trigger an SPI burst if used.