Motorola MC68VZ328 - Manual (Page 119)

DRAM Controller Operation
DRAM Controller 7-9
7.2.5 8-Bit Mode
From the system integration module (SIM), 8-bit operation on the fly can be selected using the signal 8-bit
port. If one of the CSDx signals is programmed as 8-bit mode, the 8-bit mode signal will be active at the
same time that CSDx is active. In 8-bit mode, the DRAM address multiplexer will use PA0 instead of PA1
as the least significant multiplexed address, and the remainder of the multiplexed address lines will be
adjusted to fit the 8-bit operation of the selected DRAM device. RAS, CAS, and refresh signal functions
will remain the same. Depending on the DRAM type used, the system software may need to adjust the
address multiplexer options in the DRAMMC register.
7.2.6 Low-Power Standby Mode
If DRAM that supports self-refresh mode is being used, the RM bit in the DRAMC register can be
programmed to self-refresh mode before entering sleep mode. The DRAM controller will generate one
CAS-before-RAS cycle, negate RAS and CAS for the required precharge time, then assert
CAS-before-RAS, and continue to assert them until the mode is changed in the RM bit. DRAMs that
support self-refresh mode will enter self-refresh typically 100
µ
s after RAS and CAS are held in the
asserted state. After a wake up, one CAS-before-RAS refresh cycle will occur, and then normal-mode
operation will continue.
For DRAMs without self-refresh mode, ensure that the LPR bit in the DRAMC register is set for
CAS-before-RAS refresh mode to continue while the processor is shut down and all other modules are
disabled.