Motorola MC68VZ328 - Manual (Page 371)

Index Index-xiii
interrupt controller, 9-7 to 9-19
LCD controller, 8-10 to 8-22
PWM 1, 15-4 to 15-7
PWM 2, 15-8 to 15-10
SPI 1, 13-4 to 13-11
SPI 2, 13-14 to 13-16
system control, 5-2 to 5-6
UARTs, 14-10 to 14-30
PROT bit, 4-10
Protect bit bit, see PROT bit
Pull-down field, see PDx field
Pull-down resistors, see I/O ports
Pull-up field, see PUx field
Pull-up resistors, see I/O ports
Pull-up/pull-down enable field, see PUx field
Pulse width 7–0 field, see PWx field
Pulse-width modulator 1, see PWM 1
Pulse-width modulator 2 interrupt bit, see PWM2 bit
Pulse-width modulator 2, see PWM 2
Pulse-width modulators, see PWM, PWM 1, and
PWM 2
PUx field
PAPUEN register, 10-8
PBPUEN register, 10-11
PDPUEN register, 10-18
PEPUEN register, 10-23
PFPUEN register, 10-27
PGPUEN register, 10-30
PJPUEN register, 10-33
PKPUEN register, 10-36
PMPUEN register, 10-39
PWM
clock signals, 15-2
clock source selection, 15-2
introduction, 15-1
modes of operation, 15-3
period frequency, calculating, 15-7
programming model, 15-4
signals
PWM output 1, see PWMO1/PB7 pin
PWM output 2, see
PWMO2/DATA_READY/PK0 pin
PWM 1
compared to PWM 2, 15-8
D/A mode, 15-3
description, 15-2
playback mode
digital sample values, 15-3
introduction, 15-3
maskable interrupt generation, 15-3
variable pulse width, 15-3
tone mode, 15-3
PWM 1 control register, see PWMC1 register
PWM 1 counter register, see PWMCNT1 register
PWM 1 interrupt bit, see PWM1 bit
PWM 1 period register, see PWMP1 register
PWM 1 sample register, see PWMS1 register
PWM 2
compared to PWM 1, 15-8
period register, setting to $00, 15-9
width and period settings, 15-10
PWM 2 counter register, see PWMC2 register
PWM 2 period register, see PWMP2 register
PWM 2 pulse width control register, see PWMW2
register
PWM contrast control register, see PWMR register
PWM counter input clock selection, see SRC1–0 field
PWM enable bit, see PWMEN bit
PWM interrupt bit, see PWMIRQ bit
PWM1 bit, 9-14, 9-18
PWM2 bit, 9-13, 9-17
PWMC1 register, 15-4
PWMC2 register, 15-8
PWMCNT1 register, 15-7
PWMEN bit, 15-9
PWMIRQ bit, 15-8
PWMO1/PB7 pin, 2-9
PWMO2/DATA_READY/PK0 pin, 2-9
PWMP1 register, 15-7
PWMP2 register, 15-9
PWMR register, 8-20
PWMS1 register, 15-6
PWMW2 register, 15-10
PWx field, 8-21
Q
Q counter field, see QC field
QC field, 4-10
R
Read-only bit, see RO bit
Read-only for protected memory block bit, see ROP bit
Real-time clock interrupt request bit, see RTC bit
Real-time interrupt pending (real-time clock) bit, see
RTI bit
Real-time interrupt status (real-time clock) bit, see RTI
bit
Receive polarity bit, see RXPOL bit
Receiver (UART)
FIFO buffer operation, 14-6
operation, general, 14-6
Receiver enable bit, see RXEN bit
Receiver full enable bit, see RXFE bit
Receiver half enable bit, see RXHE bit
Receiver ready enable bit, see RXRE bit
REF field, 7-13
REF_ON bit, 8-21