3 spi 2 control/status register, Spi 2 control/status register -15, Table 13-8 – Motorola MC68VZ328 User Manual
Page 251: Spi 2 control/status register description -15
SPI 2 Programming Model
Serial Peripheral Interface 1 and 2
13-15
13.6.3
SPI 2 Control/Status Register
The SPI 2 control/status (SPICONT2) register controls how the SPI 2 module operates and reports its
status. The bit position assignments for this register are shown in the following register display. The
settings for this register are described in Table 13-8.
SPICONT2
SPI 2 Control/Status Register
0x(FF)FFF802
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT
0
DATA RATE
ENABLE
XCH
IRQ
IRQEN
PHA
POL
BIT COUNT
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 13-8. SPI 2 Control/Status Register Description
Name
Description
Setting
DATA RATE
Bits 15–13
Data Rate—This field selects the bit rate of the
SPICLK2 signal based on the division of the
system clock. The master clock for the SPI 2
module is SYSCLK.
000 = Divide SYSCLK by 4.
001 = Divide SYSCLK by 8.
010 = Divide SYSCLK by 16.
011 = Divide SYSCLK by 32.
100 = Divide SYSCLK by 64.
101 = Divide SYSCLK by 128.
110 = Divide SYSCLK by 256.
111 = Divide SYSCLK by 512.
Reserved
Bits 12–10
Reserved
These bits are reserved and should be set to 0.
ENABLE
Bit 9
Enable—This bit enables the SPI 2 module.
This bit must be asserted before initiating an
exchange and should be deasserted after the
exchange is complete.
0 = The SPI 2 module is disabled.
1 = The SPI 2 module is enabled.
XCH
Bit 8
Exchange—This bit triggers a data exchange
and remains set while the exchange is in
progress. During the busy period, the
SPIDATA2 register cannot be written.
0 = Idle.
1 = Initiate an exchange (write) or busy (read).
IRQ
Bit 7
Interrupt Request—This bit is set when an
exchange is finished. If the IRQEN bit is set, an
interrupt is generated. The MSPI bit of the
interrupt mask register must be cleared for the
interrupt to be posted to the core. See
Section 9.6.3, “Interrupt Mask Register,” on
page 9-10 for more information. This bit
remains asserted until it is cleared by writing a
0. You can write a 1 to this bit to generate an
interrupt request for system debugging.
0 = An exchange is in progress or idle.
1 = The exchange is complete.