Motorola MC68VZ328 - Manual (Page 226)

12-2 MC68VZ328 User’s Manual
GP Timer Overview
12.1.1 Clock Source and Prescaler
The clock source for each timer is individually selectable through software. The selected clock source is
fed to a prescaler that acts as a divider with a programmable division ratio ranging from 1 to 256. The
output of each prescaler drives its respective counter.
The clock sources are SYSCLK, SYSCLK/16, CLK32, and an external clock from the timer I/O pin (TIO).
The clock input source is selected by the CLKSOURCE field of the timer control registers (TCTLx). The
PRESCALER field of the timer prescaler register (TPRERx) selects the divide ratio of the input clock
(PCLK) that drives the counter. The prescaler divides the input clock by a value between 1 and 256. The
programmable prescaler allows a maximum period of 512 seconds when using a 32.768 kHz crystal
oscillator or 436 seconds using a 38.4 kHz oscillator.
Of the four clock sources, only CLK32 continues to operate while the MC68VZ328 is in sleep mode. See
Section 4.5.2, “CGM Operation During Sleep Mode,” on page 4-12 for more information on CLK32
operation during sleep mode.
NOTE:
Ensure that the timer is disabled by clearing the TEN bit in the TCTLx
register before changing either the clock source or prescaler setting.
12.1.2 Timer Events and Modes of Operation
There are two types of events that produce interrupts: compare events and capture events. Compare events
occur when the value in the counter matches the contents of the compare register. Capture events occur
when a defined transition of the TOUT/TIN pin is detected.
The counter can be programmed to run in one of two modes: restart or free-running. The
free-running/restart bit in the TCTLx register only controls how the counter operates after a compare event
occurs. It does not affect counter operation following capture events. A description of each mode follows.
12.1.2.1 Restart Mode
In restart mode, the following actions occur when the compare value in the timer compare register
(TCMPx) matches the value in the timer counter register (TCNx):
1. The counter resets to 0x0000.
2. The compare event (COMP) bit of the timer status register (TSTATx) is set.
3. The TIMERx interrupt is issued to the interrupt controller if the IRQEN bit of the TCTLx
register is set.
4. The timer counter resumes counting.
This mode is useful when you need to generate periodic events or, when it is used with the timer output
signals, audio tones.
12.1.2.2 Free-Running Mode
Free-running mode is similar in operation to restart mode, except that when a compare event occurs, the
counter continues counting without resetting to 0x0000. When 0xFFFF is reached, the counter rolls over to
0x0000 and continues counting.