7 port d interrupt request enable register, 8 port d keyboard enable register, 9 port d interrupt request edge register – Motorola MC68VZ328 User Manual
Page 190: Port d interrupt request enable register -20, Port d keyboard enable register -20, Minute stopwatch -4, Table 10-23, Table 10-24, Port d keyboard enable register description -20
10-20
MC68VZ328 User’s Manual
Programming Model
10.4.5.7
Port D Interrupt Request Enable Register
The interrupt enable bits (IQEN[3:0]) determine which INT[3:0] will generate an interrupt to the interrupt
controller module. The settings for the bit positions of PDIRQEN are shown in Table 10-23.
PDIRQEN
Port D Interrupt Request Enable Register
0x(FF)FFF41D
10.4.5.8
Port D Keyboard Enable Register
All the selected signals are active low in reference to the external pins, and those that are asserted will
generate a keyboard interrupt to the interrupt controller. When a KBENx bit is selected, the DIRx bits need
to be configured as an input. The SELx, POLx, IQENx, and IQEGx bits have no effect on the functionality
of KBENx. Deasserting the interrupt source is the only way to clear a keyboard interrupt. The settings for
the bit positions of PDKBEN are shown in Table 10-24.
PDKBEN
Port D Keyboard Enable Register
0x(FF)FFF41E
10.4.5.9
Port D Interrupt Request Edge Register
The polarity of the rising or falling edge is selected by the POLx bits. It should be noted that the edge-level
interrupt for INT[3:0] cannot be used for system wake up. The level-sensitive interrupt should be used. The
settings for the bit positions of PDIRQEG are shown in Table 10-25 on page 10-21.
BIT 7
6
5
4
3
2
1
BIT 0
IQEN3
IQEN2
IQEN1
IQEN0
TYPE
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0x00
Table 10-23. Port D Interrupt Request Enable Register Description
Name Description
Setting
Reserved
Bits 7–4
Reserved
These bits are reserved and should be set
to 0.
IQENx
Bits 3–0
Interrupt Enable—These bits select the INT[3:0]
pins that are presented to the interrupt controller.
0 = Interrupt disabled.
1 = Interrupt enabled.
BIT 7
6
5
4
3
2
1
BIT 0
KBEN7
KBEN6
KBEN5
KBEN4
KBEN3
KBEN2
KBEN1
KBEN0
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0x00
Table 10-24. Port D Keyboard Enable Register Description
Name Description
Setting
KBENx
Bits 7–0
Keyboard Enable—These bits select the INT[3:0]
pins that are presented to the interrupt controller.
0 = The keyboard interrupt is disabled.
1 = The keyboard interrupt is enabled.