Motorola MC68VZ328 - Manual (Page 169)

Programming Model
Interrupt Controller 9-19
9.6.6 Interrupt Level Register
TIMER 2, UART 2, PWM 2, and SPI 1 are new modules to the MC68VZ328 compared to the previous
version, MC68EZ328. Interrupts generated from these modules are level configurable. The interrupt level
control register (ILCR) controls the interrupt level for these interrupts.
ILCR Interrupt Level Register 0x(FF)FFF314
Programming register bits 14–12, 10–8, 6–4, and 2–0 with the values shown in Table 9-8 causes the
corresponding interrupt source to generate different interrupt levels.
After reset, each of these four interrupts is set to the default level indicated:
• TIMER2IRQ (level 3)
• UART2IRQ (level 5)
• PWM2IRQ (level 3)
• SPI2IRQ (level 6)
BIT
15
14 13 12 11 10 9 8 7 6 5 4 3 2 1
BIT
0
SPI1_LEVEL UART2_LEVEL PWM2_LEVEL TMR2_LEVEL
TYPE rw rw rw rw rw rw rw rw rw rw rw rw
RESET
0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 1
0x6533
Table 9-8. Interrupt Level Register Field Values
Interrupt Level
Value in Register Bits
14–12, 10–8, 6–4, and 2–0
Undefined level 111
Level 6 110
Level 5 101
Level 4 100
Level 3 011
Level 2 010
Level 1 001
Undefined level 000
Note: Values 000 and 111 are not allowed to be programmed into
these register bits.