Motorola MC68VZ328 - Manual (Page 121)

DRAM Controller Operation
DRAM Controller 7-11
7.2.8 Data Retention Sequence
Data is retained in the following sequence:
1. The external RESET signal is sent to the MC68VZ328.
2. The internal RESET signal is generated by synchronizing the external RESET signal with
the CLK32 signal.
3. When the internal RESET is asserted, the DRAM controller will stop the current refresh
operation and enter burst refresh mode, which is a consecutive CAS-before-RAS refresh
cycle.
4. The external RESET signal continues asserting.
5. The external RESET signal is negated.
6. The internal RESET signal is negated.
7. The DRAM controller terminates the burst CAS-before-RAS refresh cycle.
8. The internal CPCRESET signal is generated for 16 clocks to reset the DRAM controller
and the CSCx and CSDx port signals.
9. The chip is now reset.
10. The core processor programs the DRAM controller and the port pins after this reset to
resume DRAM controller operation.
NOTE:
The initialization code should program or initialize the DRAM controller
and the general-purpose I/O port signals within the DRAM’s specified
refresh time.