Motorola MC68VZ328 - Manual (Page 199)

Programming Model
I/O Ports 10-29
PGDATA Port G Data Register 0x(FF)FFF431
Port G is multiplexed with address line A0 and several dedicated I/O functions. These pins can be
programmed as GPIO when the address bus and the dedicated I/O signals are not in use.
All of the bits control or report the data on the pins while the associated SELx bits are high. While the
DIRx bits are high (output), the Dx bits control the pins. While the DIRx bits are low (input), the Dx bits
report the signal driving the pins. The Dx bits can be written at any time. Bits that are configured as inputs
will accept the data, but the data written to each cannot be accessed until the corresponding pin is
configured as an output. The actual value on the pin is reported when these bits are read, regardless of
whether they are configured as input or output. See Table 10-36 on page 10-28 for information about
setting the bits in the PGDIR register.
10.4.8.3 Port G Dedicated I/O Functions
The six PGDATA lines are multiplexed with the dedicated I/O signals whose assignments are shown in
Table 10-38.
BIT 7 6 5 4 3 2 1 BIT 0
D5 D4 D3 D2 D1 D0
TYPE rw rw rw rw rw rw
RESET
0 0 1 1 1 1 1 1
0x3F*
*Actual bit value depends on external circuits connected to pin.
Table 10-37. Port G Data Register Description
Name Description Setting
Reserved
Bits
7–6
Reserved These bits are reserved and should be set to 0.
Dx
Bits 5–0 Data—These bits reflect the
status of the I/O signal in an
8-bit system. 0 = Drives the output signal low when DIRx is set to 1 or the external
signal is low when DIRx is set to 0
1 = Drives the output signal high when DIRx is set to 1 or the external
signal is high when DIRx is set to 0
Table 10-38. Port G Dedicated I/O Function Assignments
Bit GPIO Function Dedicated I/O Function
0 Data bit 0 BUSW/DTACK
1 Data bit 1 A0
2 Data bit 2 EMUIRQ
3 Data bit 3 HIZ/P/D
4 Data bit 4 EMUCS
5 Data bit 5 EMUBRK
6
7