Motorola MC68VZ328 - Manual (Page 52)

2-10 MC68VZ328 User’s Manual
SDRAM Interface Signals
2.14 Chip-Select and EDO RAM Interface Signals
Chip-select logic is used to provide maximum compatibility with a wide variety of memory logic. This
section and Section 2.15, “SDRAM Interface Signals,” describe the signals used to interface with RAM,
SDRAM, and EDO RAM.
• CSA0—Chip-Select A bit 0. CSA0 is a default chip-select signal after reset. It is set to 6 wait states
and decodes all address ranges, except internal register address space, emulator space, and bootstrap
space (0xFFFC0000–0xFFFFFFFF). It can be reprogrammed during the boot sequence to another
address range or different wait states. The default data bus width for CSA0 is determined by the state
of the BUSW signal.
• CSA1/PF7, CSB[1:0]/PB[1:0], CSC[1:0]/PB[3:2]/RAS[1:0], CSD[1:0]/PB[5:4]/CAS[1:0]—
Chip-Select A, B, C, and D bits 0 and 1, Port F bit 7, Port B bits 5–0, or row and column select
signals. These pins comprise the remainder of the Group A, B, C, and D chip-selects and are
individually programmable. Pins that are not needed as chip-selects can be programmed as
general-purpose I/O. In addition, CSC[1:0] and CSD[1:0] are designed to support DRAM as CAS
and RAS signals. These pins default to GPIO input pulled high.
• PM5/DMOE—Port M bit 5 or DRAM Continuous Page Mode Output Enable. DMOE is similar to
the OE signal. However, DMOE only goes active on DRAM read cycles, while OE is active for all
memory read cycles. In continuous page mode, RAS is held low until a page-miss, refresh required,
or RAS duration time out. During an RAS low period there may be other memory access cycles,
and if OE is used to enable the DRAM data output, DRAM will drive data, producing bus
contention. Therefore, a dedicated output enable, DMOE, is required, connecting to DRAM if
continuous page mode is enabled. Using this mode will minimize the number of clocks per DRAM
access. This pin defaults to GPIO input pulled high.
2.15 SDRAM Interface Signals
• CSD0, CSD1—These two signals are multiplexed with SDRAM CS0 and CS1. When SDRAM is
enabled, CSD0 and CSD1 are SDRAM bank 1 and bank 2 chip-select signals. Also see Chapter 6,
“Chip-Select Logic,” for more details.
• CSC0—This signal is multiplexed with SDRAM RAS. When SDRAM is enabled, this signal
becomes an SDRAM RAS signal. For additional information about this subject, see Chapter 6,
“Chip-Select Logic.”
• CSC1—This signal is multiplexed with SDRAM CAS. When SDRAM is enabled, this signal
becomes an SDRAM RAS signal. For more details, see Chapter 6, “Chip-Select Logic.”
• SDWE—SDRAM WE. When SDRAM is enabled, this signal becomes an SDRAM Write-Enable
signal. There is additional programming information about this subject in Chapter 6, “Chip-Select
Logic.”
• PM0/SDCLK—Port M bit 0 or SDRAM Clock. This pin defaults to GPIO input pulled low.
• PM1/SDCE—Port M bit 1 or SDRAM Clock Enable. This pin defaults to GPIO pulled low.
• PM2/DQMH, PM3/DQML—Port M bits 2–3 or SDRAM input/output mask. These pins default to
GPIO pulled low.
• PM4/SDA10—Port M bit 4 or SDRAM Address A10. This pin defaults to GPIO input pulled low.