2 pwm 2 period register, Pwm 2 period register -9, Table 15-6 – Motorola MC68VZ328 User Manual
Page 291: Pwm 2 period register description -9
PWM 2
Pulse-Width Modulator 1 and 2
15-9
15.5.2
PWM 2 Period Register
This register controls the period of PWM 2. When the counter value matches the value, an interrupt is
generated and the counter is reset to start another period. The register bit assignments are shown in the
following register display. The register settings are described in Table 15-6.
PWMP2
PWM 2 Period Register
0x(FF)FFF512
NOTE:
There is an special case: when the register is set to $00, the output will
never go high. The pulse signal duty cycle will be 0 percent.
PIN
Bit 7
Pin Status Indicator—This bit indicates the current status of the
PWM.
0 = PWM output is high.
1 = PWM output is low.
Reserved
Bit 6
Reserved
This bit is reserved and
should be set to 0.
POL
Bit 5
Output Polarity—This bit controls the PWM output polarity.
0 = Normal polarity.
1 = Inverted polarity.
PWMEN
Bit 4
PWM Enable—This bit enables PWM 2.
0 = PWM 2 disabled.
1 = PWM 2 enabled.
Reserved
Bit 3
Reserved
This bit is reserved and
should be set to 0.
CLKSEL
Bits 2–0
Clock Selection—These bits select the output of the divider
chain.
000 = Divide by 4.
001 = Divide by 8.
010 = Divide by 16.
011 = Divide by 32.
100 = Divide by 64.
101 = Divide by 128.
110 = Divide by 256.
111 = Divide by 512.
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT
0
PERIOD
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 15-6. PWM 2 Period Register Description
Name Description Setting
PERIOD
Bits 15–0
Period—This field represents the pulse-width modulator’s period control value.
None
Table 15-5. PWM 2 Control Register Description (Continued)
Name Description
Setting