Motorola MC68VZ328 - Manual (Page 231)

Programming Model
General-Purpose Timers 12-7
CAP
Bits 7–6 Capture Edge—This field selects the type of
transition on the TIN input that triggers a cap-
ture event.
Note: To use TIN/TOUT as a TIN input,
ensure that the SEL6 bit in the Port B select
register (PBSEL) is cleared.
00 = Disable capture function (default).
01 = Capture on rising edge.
10 = Capture on falling edge.
11 = Capture on rising or falling edges.
OM
Bit 5 Output Mode—This bit selects the output
mode of the timer after a compare event
occurs. The output appears for one SYSCLK
period. 0 = Active-low pulse (default).
1 = Toggle output.
IRQEN
Bit 4 Interrupt Request Enable—This bit enables
an interrupt on a compare event. 00 = Disable the compare interrupt (default).
01 = Enable the compare interrupt.
CLKSOURCE
Bit 3–1 Clock Source—This field controls the clock
source to the prescaler. The stop count
freezes the counter at its current value.
Note: To use TIN/TOUT as a TIN input,
ensure that the SEL6 bit in the Port B select
register (PBSEL) is cleared. Also ensure that
DIR6 = 0.
000 = Stop counter (default).
001 = SYSCLK to prescaler.
010 = SYSCLK/16 to prescaler.
011 = TIN to prescaler.
1xx = CLK32 to prescaler.
TEN
Bit 0 Timer Enable—This bit enables or disables
the associated timer. 0 = Timer is disabled (default).
1 = Timer is enabled.
Table 12-2. Timer Control Register Description (Continued)
Name Description Setting