Motorola MC68VZ328 - Manual (Page 266)

14-14 MC68VZ328 User’s Manual
Programming Model
14.4.4 UART 1 Transmitter Register
The UART 1 transmitter (UTX1) register controls how the transmitter operates. The bit position
assignments for this register are shown in the following register display. The settings for this register are
described in Table 14-7.
UTX1 UART 1 Transmitter Register 0x(FF)FFF906
FRAME
ERROR
Bit 10 Frame Error (Character Status)—This read-only bit indicates
that the current character had a framing error (missing stop bit),
which indicates that there may be corrupted data. This bit is
updated for each character read from the FIFO. 0 = Character has no framing error
1 = Character has a framing error
BREAK
Bit 9 Break (Character Status)—This read-only bit indicates that
the current character was detected as a BREAK. The data bits
are all 0 and the stop bit is also 0. The FRAME ERROR bit will
always be set when this bit is set, and if odd parity is selected,
PARITY ERROR will also be set. This bit is updated and valid
with each character read from the FIFO. 0 = Character is not a break
character
1 = Character is a break character
PARITY
ERROR
Bit 8 Parity Error (Character Status)—This read-only bit indicates
that the current character was detected with a parity error,
which indicates that there may be corrupted data. This bit is
updated and valid with each character read from the FIFO.
While parity is disabled, this bit always reads 0. See description
RX
DATA
Bits 7–0 Rx Data (Character Data)—This read-only field is the top
receive character in the FIFO. The bits have no meaning if the
DATA READY bit is 0. In 7-bit mode, the most significant bit is
forced to 0, and in 8-bit mode, all bits are active. See description
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
BIT
0
FIFO
EMPTY
FIFO
HALF
TX
AVAI
L
SEND
BREAK
NO
CTS1
BUSY
CTS1
STAT CTS1
DELTA
TX DATA
TYPE r r r rw rw rw rw rw w w w w w w w w
RESET
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0x0000
Table 14-7. UART 1 Transmitter Register Description
Name Description Setting
FIFO
EMPTY
Bit 15 FIFO Empty (FIFO Status)—This read-only bit indicates that
the transmitter FIFO is empty. This bit generates a maskable
interrupt. 0 = Transmitter FIFO is not empty
1 = Transmitter FIFO is empty
Table 14-6. UART 1 Receiver Register Description (Continued)
Name Description Setting