Motorola MC68VZ328 - Manual (Page 364)

Index-vi MC68VZ328 User’s Manual
Frame marker polarity bit, see FLMPOL bit
Frame rate modulation, absence of control function, 8-7
Free-running/restart bit, see FRR bit
FRR bit, 12-6
Full address decode enable bit, see UGEN bit
G
G13–G10 field, 8-20
G23–G20 field, 8-20
GBAx field, 6-4
GBBx field, 6-5
GBCx field, 6-5
GBDx field, 6-6
General-purpose timers, see GP timers
GP timers
block diagram, 12-1
changing clock source, precautions, 12-2
clock sources, 12-2
description, 12-1
events
capture events, 12-2
compare events, 12-2
interrupt events, 12-2
modes
counter modes of operation, 12-2
free-running mode, 12-2
restart mode, 12-2
sleep mode, CLK32 operation, 12-2
programming model, 12-6 to 12-12
GPIO
assigning pins as, 10-1
configuring pull-up resistors, 10-1
Grayscale 13–10 field, see G13–G10 field
Grayscale 23–20 field, see G23–G20 field
Grayscale mode selection 1–0 field, see GSx field
Group A base address field, see GBAx field
Group B base address field, see GBBx field
Group base address registers
group A base address register, see CSGBA register
group B base address register, see CSGBB register
group C base address register, see CSGBC register
group D base address register, see CSGBD register
upper group base address register, see CSUGBA
register
using, 6-4
Group C base address field, see GBCx field
Group D base address field, see GBDx field
GSx field, 8-15
H
Hardware flow control, UART, see CTS signal
HASL finish, see PCB finish requirements
HMARK register, 14-29
I
I/O ports
configuration, 10-1
data flow from I/O module, 10-4
data flow to I/O module, 10-5
data loss when changing modes, preventing, 10-5
dedicated functions, 10-2
drive current levels, setting, 10-1
introduction, 10-1
operating port as GPIO, 10-5
operation, 10-4 to 10-6
pin names, understanding, 10-1
programming model, 10-6 to 10-40
pull-down resistors, 10-6
pull-up resistors, 10-6
select registers, using, 10-1
ICE module
A-line insertion unit, 16-3
application development design example, 16-14
block diagram, 16-1
clearing interrupts, 16-3
dedicated debug monitor memory, 16-11
detecting breakpoints, 16-2
emulation memory mapping, 16-12
emulation mode, starting, 16-2
exception vector fetch, 16-2
execution and bus breakpoints compared, 16-3
execution breakpoint, 16-2
FPGA address comparator, 16-12
host interface, 16-11
interrupt gate module, using, 16-3
introduction, 16-1
operation, 16-2
plug-in emulator design example, 16-12
programming example, 16-10
programming model, 16-4 to 16-14
registers
address compare register, see ICEMACR
register
address mask register, see ICEMAMR register
control compare register, see ICEMCCR
register
control mask register, see ICEMCMR register
control register, see ICEMCR register
status register, see ICEMSR register
reset vector, 16-2
signal decoder, 16-3
signals, 2-11
trace module, 16-12
ICEMACR register, 16-5
ICEMAMR register, 16-5
ICEMCCR register, 16-6
ICEMCMR register, 16-6