2 timer prescaler registers 1 and 2, Timer prescaler registers 1 and 2 -8, Table 12-3 – Motorola MC68VZ328 User Manual
Page 232: Timer prescaler register description -8
12-8
MC68VZ328 User’s Manual
Programming Model
12.2.2
Timer Prescaler Registers 1 and 2
Each timer prescaler register (TPRERx) controls the divide ratio of the associated prescaler. The settings
for the registers are described in Table 12-3.
TPRER1
Timer Prescaler Register 1
0x(FF)FFF602
TPRER2
Timer Prescaler Register 2
0x(FF)FFF612
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
Not Used
Prescaler
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
Not Used
Prescaler
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 12-3. Timer Prescaler Register Description
Name Description
Setting
Not used
Bits 15–8
These bits are not used.
—
PRESCALER
Bits 7–0
Prescaler—This field controls the frequency
output of the prescaler. The clock source is
divided by the value contained in this register.
The value range of this field is between 1 and
256.
0x00 = Divide by 1
.
.
.
0xFF = Divide by 256