Motorola MC68VZ328 - Manual (Page 373)

Index Index-xv
SB bit, 16-8
SCR register, 5-2
Screen starting address 31–1 field, see SSAx field
SDRAM interface signals, 2-10
SDRAM, selecting multiplexing options, 7-5 to 7-6
SDRAM–to–MC68VZ328 connections,
recommendations, 7-5 to 7-6
SELECT field
NIPR1 register, 14-18
NIPR2 register, 14-28
Self-refresh mode, see LCD controller
Self-refresh on bit, see REF_ON bit
SELx field
PBSEL register, 10-11
PCSEL register 10-14
PDSEL register, 10-19
PESEL register, 10-23
PFSEL register, 10-27
PGSEL register, 10-31
PJSEL register, 10-33
PKSEL register, 10-36
PMSEL register, 10-40
Send break (Tx control) bit, see SEND BREAK bit
SEND BREAK bit
UTX1 register, 14-15
UTX2 register, 14-25
Serial peripheral interface 1 signals, see SPI 1
Serial peripheral interface 1, see SPI 1
Serial peripheral interface 2 signals, see SPI 2
Serial peripheral interface 2, see SPI 2
Serial peripheral interface, see SPI, SPI 1, and SPI 2
Signals
CLKO, 2-4
clock and system control, 2-4
grouped by function, block diagram, 2-2
grouped by function, table, 2-3
introduction, 2-1
power and ground signals, 2-4
XTAL, 2-4
Single breakpoint bit, see SB bit
SIZ field
CSA register, 6-9
CSB register, 6-11
CSC register, 6-13
CSD register, 6-15
Size bit 3 for DRAM chip-select addressing space, see
DSIZ3 bit
Sleep mode
events occuring during sleep mode, 4-12
operation, 4-12
Slow multiplexing bit, see MSW bit
Slow RAM bit, see SLW bit
SLW bit, 7-15
SOP bit
CSB register, 6-10
CSC register, 6-12
CSD register, 6-14
Source field, see SRC1–0 field
SPI 1
block diagram, 13-1
data
bad data word indication, 13-9
ensuring none is lost, 13-9
transferring between devices, 13-2
overview, 13-1
phase and polarity, 13-3
programming model, 13-4 to 13-11
registers
control and status register, see SPICONT1
register,
interrupt control/status register, see SPIINTCS
register
receive data register, see SPIRXD register
sample period control register, see SPISPC
register
test register, see SPITEST register
transmit data register, see SPITXD register
RxFIFO, top of, see DATA field
signals
master in/slave out, see MISO signal
master out/slave in, see MOSI signal
slave select, see SS signal
SPI clock, see SPICLK1 signal
SPI data ready, see DATA_READY signal
SPI receive data, see MISO/PJ1 pin
SPI transmit data, see MOSI/PJ0 pin
SPICLK1 polarity, configuring, 13-3
timing diagrams
control signals, 19-32 to 19-34
generic, 13-2, 19-32
using as master, 13-2
using as slave, 13-2
writing to TxFIFO
denied, 13-5
when permitted, 13-5
SPI 1 enable bit, see SPIEN bit
SPI 1 interrupt pending bit, see SPI1 bit
SPI 1 interrupt status bit, see SPI1 bit
SPI 1 mode select bit, see MODE bit
SPI 2
debugging, generating an interrupt for, 13-15
operation, 13-12
overview, 13-11
phase 0 operation, 13-13
phase 1 operation, 13-13
phase and polarity configuration, 13-13
programming model, 13-14 to 13-16