Motorola MC68VZ328 - Manual (Page 159)

Programming Model
Interrupt Controller 9-9
ET2
Bit 10 IRQ2 Edge Trigger Select—When this bit is set, the IRQ2 signal is an
edge-triggered interrupt. In edge-triggered mode, a 1 must be written to the
IRQ2 bit in the interrupt status register to clear this interrupt. When this bit is
low, IRQ2 is a level-sensitive interrupt. In this case, the external source of the
interrupt must be cleared. 0 = Level-sensitive
interrupt.
1 = Edge-sensitive
interrupt.
ET3
Bit 9 IRQ3 Edge Trigger Select—When this bit is set, the IRQ3 signal is an
edge-triggered interrupt. In edge-triggered mode, a 1 must be written to the
IRQ3 bit in the interrupt status register to clear this interrupt. When this bit is
low, IRQ3 is a level-sensitive interrupt. In this case, the external source of the
interrupt must be cleared. 0 = Level-sensitive
interrupt.
1 = Edge-sensitive
interrupt.
ET6
Bit 8 IRQ6 Edge Trigger Select—When this bit is set, the IRQ6 signal is an
edge-triggered interrupt. In edge-triggered mode, a 1 must be written to the
IRQ6 bit in the interrupt status register to clear this interrupt. When this bit is
low, IRQ6 is a level-sensitive interrupt. In this case, the external source of the
interrupt must be cleared. 0 = Level-sensitive
interrupt.
1 = Edge-sensitive
interrupt.
POL5
Bit 7 Polarity Control 5—This bit controls interrupt polarity for the IRQ5 signal. In
level-sensitive mode, negative polarity produces an interrupt when the signal is
at logic level low. Positive polarity produces an interrupt when the signal is at
logic level high. In edge-triggered mode, negative polarity produces an interrupt
when the signal goes from logic level high to logic level low. Positive polarity
generates an interrupt when the signal goes from logic level low to logic level
high. 0 = Negative
polarity.
1 = Positive
polarity.
Reserved
Bits 6–0 Reserved These bits are
reserved and
should remain at
their default value.
Note: Clear interrupts after changing modes. When modes are changed from level to edge interrupts, an edge
can be created, which causes an interrupt to be posted.
Table 9-4. Interrupt Control Register Description (Continued)
Name Description Setting