Motorola MC68VZ328 - Manual (Page 188)

10-18 MC68VZ328 User’s Manual
Programming Model
10.4.5.3 Port D Interrupt Options
Interrupt bits 3–0 (INT[3:0]), interrupt request bits 3–1 (IRQ[3:1]), interrupt request bit 6 (IRQ6), or Port
D bits 7–0 can be configured as edge- or level-triggered interrupt signals.
NOTE:
When external interrupts INT[3:0], IRQ1, IRQ2, IRQ3, and IRQ6 are
programmed as edge-triggered interrupts, they can be cleared by writing a
1 to the corresponding status bit in the interrupt status register in the
interrupt controller. When programmed as level-triggered interrupts, these
interrupts are cleared at the requesting sources.
To support keyboard applications, the I/O function can be used with interrupt capabilities, which are
described in Chapter 9, “Interrupt Controller.”
The individual interrupt bits can be masked on a bit-by-bit basis. The KB is enabled or disabled by the
KBENx bits of the PDKBEN register. Individual interrupts can be configured as either edge- or
level-sensitive by asserting or clearing the IQEGx bits of the PDIRQEG register. Likewise, the polarity of
the interrupt is determined by the POLx bits of the PDPOL register.
All of the interrupt signals in the table can be used as system wake-up interrupts, except for the edge
interrupt on INT[3:0]. Edge interrupts on INT[3:0] can only interrupt the CPU when the system is awake.
The INT[3:0] signals are all level 4 interrupts, but IRQx has its own level. Any combination of Port D
signals and OR (negative logic) can be selected to generate keyboard (KB) interrupts to the CPU. The KBx
signal is an active low, level-sensitive interrupt of the selected pins. Like the other ports, each pin can be
configured as an input or output on a bit-by-bit basis. When they are configured as inputs, each pin can
generate a CPU interrupt.
10.4.5.4 Port D Pull-up Enable Register
The Port D pull-up enable register (PDPUEN) controls the pull-up resistors for each line in Port D. The
settings for the bit positions in PDPUEN are shown in Table 10-20.
PDPUEN Port D Pull-up Enable Register 0x(FF)FFF41A
BIT 7 6 5 4 3 2 1 BIT 0
PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
TYPE rw rw rw rw rw rw rw rw
RESET
1 1 1 1 1 1 1 1
0xFF
Table 10-20. Port D Pull-up Enable Register Description
Name Description Setting
PUx
Bits 7–0 Pull-up—These bits enable the pull-up resistors on the port. 0 = Pull-up resistors are disabled
1 = Pull-up resistors are enabled