11 pulse-width modulator signals, 12 serial peripheral interface 1 signals, 13 serial peripheral interface 2 signals – Motorola MC68VZ328 User Manual
Page 51: Pulse-width modulator signals -9, Serial peripheral interface 1 signals -9, Serial peripheral interface 2 signals -9
Serial Peripheral Interface 2 Signals
Signal Descriptions
2-9
2.11
Pulse-Width Modulator Signals
There are two pulse-width modulator (PWM) modules in the MC68VZ328. This section describes the
signals available to communicate with these PWM modules.
•
PWMO1/PB7—Pulse-Width Modulator Output 1 or Port B bit 7. PWMO1 is an output signal from
the logical operation (AND or OR) of both the PWM 1 and PWM 2 modules. This pin defaults to
GPIO input pulled high.
•
PWMO2/DATA_READY/PK0—Pulse-Width Modulator Output 2, SPI Data Ready, or Port K bit 0.
PWMO2 is an output signal from the PWM 2 module. If this pin is configured for dedicated I/O
function and PKDIR0 is 1, the PWMO2 signal is selected. If PKDIR0 is 0, SPI Data Ready
(DATA_READY) is selected. This pin defaults to GPIO input pulled high.
2.12
Serial Peripheral Interface 1 Signals
There are two serial peripheral interface (SPI) modules in the MC68VZ328. This section describes the
signals that are used with SPI 1 to interface with external devices.
•
MOSI/PJ0—SPI Transmit Data or Port J bit 0. MOSI is the master output/slave input signal for the
SPI shift register. This pin defaults to GPIO input pulled high.
•
MISO/PJ1—SPI Receive Data or Port J bit 1. MISO is the master input/slave output signal for the
SPI shift register. This pin defaults to GPIO input pulled high.
•
SPICLK1/PJ2—SPI Clock or Port J bit 2. SPICLK1 is the master clock output/slave clock input
signal for SPI. In polarity = 0 mode, this signal is low while the serial peripheral interface master is
idle. In polarity = 1 mode, this signal is high during idle. This pin defaults to GPIO input pulled
high.
•
SS/PJ3—SPI Slave Select or Port J bit 3. SS is the master output/slave input chip-select signal. This
pin defaults to GPIO input pulled high.
•
DATA_READY/PWMO2/PK0—SPI Data Ready or Port K bit 0. DATA_READY can be used in
master mode to signal the SPI master to clock out data. To select the DATA_READY function, the
PKDIR0 and PKSEL0 bits are written 0. This pin defaults to GPIO input pulled high.
2.13
Serial Peripheral Interface 2 Signals
This section describes the signals that are used with SPI 2, the second serial peripheral interface (SPI)
module in the MC68VZ328, to interface with external devices.
•
SPITXD/PE0—SPI Master Transmit Data or Port E bit 0. SPITXD is the master SPI shift register
output signal. This pin defaults to GPIO input pulled high.
•
SPIRXD/PE1—SPI Master Receive Data or Port E bit 1. SPIRXD is the input to the master SPI shift
register. This pin defaults to GPIO input pulled high.
•
SPICLK2/PE2—SPI Master Clock or Port E bit 2. SPICLK2 is the clock output when the serial
peripheral interface master is enabled. In polarity = 0 mode, this signal is low while the serial
peripheral interface master is idle. In polarity = 1 mode, this signal is high during idle. This pin
defaults to GPIO input pulled high.