Motorola MC68VZ328 - Manual (Page 163)

Programming Model
Interrupt Controller 9-13
RTI
Bit 22 Real-Time Interrupt Status (Real-Time Clock)—When set, this bit
indicates that the real-time timer has reached its predefined fre-
quency count. The frequency can be selected inside the real-time
clock module, which can function as an additional timer. 0 = Real-time timer has not
reached predefined
frequency count.
1 = Real-time timer has
reached predefined
frequency count.
SPI1
Bit 21 SPI 1 Interrupt Status—When set, this bit indicates an interrupt
event from SPI unit 1. 0 = No SPI 1 interrupt is
pending.
1 = An SPI 1 interrupt is
pending.
IRQ5
Bit 20 Interrupt Request Level 5—This bit, when set, indicates that an
external device is requesting an interrupt on level 5. If the IRQ5 sig-
nal is set to be a level-sensitive interrupt, the source of the interrupt
must first be cleared. 0 = No level 5 interrupt is
pending.
1 = A level 5 interrupt is
pending.
IRQ6
Bit 19 Interrupt Request Level 6—This bit, when set, indicates that an
external device is requesting an interrupt on level 6. If the IRQ6 sig-
nal is set to be a level-sensitive interrupt, the source of the interrupt
must first be cleared. If IRQ6 is set to be an edge-triggered interrupt,
the interrupt must be cleared by writing a 1 to this bit. Writing a 0 to
this bit has no effect. 0 = No level 6 interrupt is
pending.
1 = A level 6 interrupt is
pending.
IRQ3
Bit 18 Interrupt Request Level 3—This bit, when set, indicates that an
external device is requesting an interrupt on level 3. If the IRQ3 sig-
nal is set to be a level-sensitive interrupt, the source of the interrupt
must first be cleared. If IRQ3 is set to be an edge-triggered interrupt,
the interrupt must be cleared by writing a 1 to this bit. Writing a 0 to
this bit has no effect. 0 = No level 3 interrupt is
pending.
1 = A level 3 interrupt is
pending.
IRQ2
Bit 17 Interrupt Request Level 2—This bit, when set, indicates that an
external device is requesting an interrupt on level 2. If the IRQ2 sig-
nal is set to be a level-sensitive interrupt, the source of the interrupt
must first be cleared. If IRQ2 is set to be an edge-triggered interrupt,
the interrupt must be cleared by writing a 1 to this bit. Writing a 0 to
this bit has no effect. 0 = No level 2 interrupt is
pending.
1 = A level 2 interrupt is
pending.
IRQ1
Bit 16 Interrupt Request Level 1—This bit, when set, indicates that an
external device is requesting an interrupt on level 1. If the IRQ1 sig-
nal is set to be a level-sensitive interrupt, the source of the interrupt
must first be cleared. If IRQ1 is set to be an edge-triggered interrupt,
the interrupt must be cleared by writing a 1 to this bit. Writing a 0 to
this bit has no effect. 0 = No level 1 interrupt is
pending.
1 = A level 1 interrupt is
pending.
Reserved
Bits 15–14 Reserved These bits are reserved
and should be set to 0.
PWM2
Bit 13 Pulse-Width Modulator 2 Interrupt—This bit indicates that an
interrupt event from PWM unit 2 is pending. The interrupt level is
configurable from level 1 to level 6. See Section 9.6.6, “Interrupt
Level Register,” for more details. 0 = No PWM 2 interrupt is
pending.
1 = A PWM 2 interrupt is
pending.
Table 9-6. Interrupt Status Register Description (Continued)
Name Description Settings