Motorola MC68VZ328 - Manual (Page 160)

9-10 MC68VZ328 User’s Manual
Programming Model
9.6.3 Interrupt Mask Register
The interrupt mask register (IMR) can mask out a particular interrupt if the corresponding bit for the
interrupt is set. There is one control bit for each interrupt source. When an interrupt is masked, the interrupt
controller will not generate an interrupt request to the CPU, but its status can still be observed in the
interrupt pending register. At reset, all the interrupts are masked and all the bits in this register are set to 1.
IMR Interrupt Mask Register 0x(FF)FFF304
BIT
31
30 29 28 27 26 25 24 23 22 21 20 19 18 17
BIT
16
ME
MIQ
MR
TI
MS
PI1 MIR
Q5
MIR
Q6
MIR
Q3
MIR
Q2
MIR
Q1
TYPE rw rw rw rw rw rw rw rw
RESET
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0x00FF
BIT
15
14 13 12 11 10 9 8 7 6 5 4 3 2 1
BIT
0
MP
WM
2
MU
AR
T2
MI
NT
3
MI
NT
2
MI
NT
1
MI
NT
0
MP
WM
1
MK
B
MT
MR
2
MR
TC
MW
DT
MU
AR
T1
MT
MR
1
MS
PI2
TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw
RESET
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0xFFFF
Table 9-5. Interrupt Mask Register Description
Name Description Settings
Reserved
Bits 31–24 Reserved These bits are reserved and should
be set to 0.
MEMIQ
Bit 23 Mask Emulator Interrupt—When set, this bit indicates that
the EMUIRQ pin and in-circuit emulation breakpoint interrupt
functions are masked. It is set to 1 after reset. These inter-
rupts are level 7 interrupts to the CPU. 0 = Enable EMUIRQ interrupt
1 = Mask EMUIRQ interrupt
MRTI
Bit 22 Timer for Real-Time Clock—When set, this bit indicates
that the real-time interrupt timer is masked. It is set to 1 after
reset. 0 = Enable real-time interrupt timer
interrupt.
1 = Masked real-time interrupt
timer interrupt.
MSPI1
Bit 21 Mask SPI1 Interrupt—When set, this bit indicates that the
SPI 1 interrupt is masked. It is set to 1 after reset. 0 = Enable SPI 1 interrupt.
1 = Mask SPI 1 interrupt.
MIRQ5
Bit 20 Mask IRQ5 Interrupt—When set, this bit indicates that IRQ5
is masked. It is set to 1 after reset. 0 = Enable IRQ5 interrupt.
1 = Mask IRQ5 interrupt.
MIRQ6
Bit 19 Mask IRQ6 Interrupt—When set, this bit indicates that IRQ6
is masked. It is set to 1 after reset. 0 = Enable IRQ6 interrupt.
1 = Mask IRQ6 interrupt.
MIRQ3
Bit 18 Mask IRQ3 Interrupt—When set, this bit indicates that IRQ3
is masked. It is set to 1 after reset. 0 = Enable IRQ3 interrupt.
1 = Mask IRQ3 interrupt.