Motorola MC68VZ328 - Manual (Page 86)

5-4 MC68VZ328 User’s Manual
Programming Model
5.2.2 Peripheral Control Register
This register controls the PWM logical block operation, timer TIN/TOUT signal, and UART UCLK
signal. The bit assignments for the register are shown in the following register display. The settings for the
bits in the register are listed in Table 5-2.
PCR Peripheral Control Register 0x(FF)FFF003
BIT 7 6 5 4 3 2 1 BIT 0
UCLK P[1:0] T[1:0]
TYPE rw rw rw rw rw
RESET
0 0 0 0 0 0 0 0
0x00
Table 5-2. Peripheral Control Register Description
Name Description Setting
Reserved
Bits 7–5 Reserved Do not use these bits.
UCLK
Bit 4 UART Clock Pin Configuration—When UCLK
of UART 1 and UART 2 is configured to output
signal, this bit selects UART 1’s or UART 2’s
UCLK for UCLK pin output. When UCLK of
UART 1 and UART 2 is configured as input, this
bit is “don’t care,” and UCLK pin is an input signal. 0 = UCLK pin is connected to UART 1.
1 = UCLK pin is connected to UART 2.
P[1:0]
Bits 3–2 PWM Outputs Logic Operation—These bits
select the logical combination for final PWM pin
output. 00 = 8-bit PWM out only (default).
01 = 16-bit PWM out only.
10 = Logic OR of both PWM outputs.
11 = Logic AND of both PWM outputs.
T[1:0]
Bits 1–0 TIN/TOUT Signal Configuration—These 2 bits
are used to configure the external TIN/TOUT sig-
nal when pin PB6/TIN/TOUT is selected as
TIN/TOUT function. For detailed information on
using this function, see Section 12.1.4,
“TOUT/TIN/PB6 Pin,” on page 12-3. 00 = TIN/TOUT is connected to Timer 1.
01 = TIN/TOUT is connected to Timer 2.
10 = Timer 2 OUT -> Timer 1 IN; TIN -> Timer 2
(DIR6 = 0), or TOUT -> Timer 1 (DIR6 = 1).
11 = Timer 1 OUT -> Timer 2 IN; TIN -> Timer 1
(DIR6 = 0), or TOUT -> Timer 2 (DIR6 = 1).