6 spi 2 programming model, 1 spi 2 data register, 2 spi 2 data register timing – Motorola MC68VZ328 User Manual
Page 250: Spi 2 programming model -14, Spi 2 data register -14, Spi 2 data register timing -14, Table 13-7, Spi 2 data register description -14
13-14
MC68VZ328 User’s Manual
SPI 2 Programming Model
13.6
SPI 2 Programming Model
This section provides information for programming SPI 2.
13.6.1
SPI 2 Data Register
The SPI 2 data (SPIDATA2) register exchanges data with external slave devices. The bit position
assignments for this register are shown in the following register display. The settings for this register are
described in Table 13-7.
SPIDATA2
SPI 2 Data Register
0x(FF)FFF800
13.6.2
SPI 2 Data Register Timing
The data bits are exchanged with the external device. The data must be loaded before the XCH bit in the
SPICONT2 register is set. In phase 0, data is presented on the SPITXD pin when this register is written. In
phase 1, the first data bit is presented on the first SPICLK2 edge. At the end of the exchange, data from the
peripheral is present in this register and bit 0 is the least significant bit. As data is shifted MSB first,
outgoing data is automatically MSB justified. For example, if the exchange length is 10 bits, the first bit
presented to the external device will be bit 9, followed by the remaining bits.
NOTE:
Writes to this field are ignored while the ENABLE bit is clear or while the
XCH bit is set. This field contains unknown data if it is read while the XCH
bit is set.
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT
0
DATA
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 13-7. SPI 2 Data Register Description
Name Description
Setting
DATA
Bits 15–0
Data—Top of SPI 2’s RxFIFO (8 × 16)
The data in this register has no meaning if the RR
bit in the interrupt control/status register is clear.