Digi NS9215 - Manual (Page 104)

W O R K I N G W I T H T H E C P U
R14 register
104 Hardware Reference NS9215
A1, A2, and A3 are the three instructions following the fast context switch.
Context ID
register
The Context ID register provides a mechanism that allows real-time trace tools to
identify the currently executing process in multi-tasking environments.
Access
instructions
Use these instructions to access the Context ID register:
Register format
This is the format of the Context ID register (Rd) transferred during this operation.
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R 1 4 r e g i s t e r
Accessing (reading or writing) this register is reserved.
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R 1 5 : T e s t a n d d e b u g r e g i s t e r
Register R15 to provides device-specific test and debug operations in ARM926EJ-S
processors. Use of this register currently is reserved.
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J a z e l l e ( J a v a )
The ARM926EJ-S processor has ARM’s embedded Jazelle Java acceleration hardware
in the core. Java offers rapid application development to software engineers.
The ARM926EJ-S processor core executes an extended ARMv5TE instruction set,
which includes support for Java byte code execution (ARMv5TEJ). An ARM optimized
Java Virtual Machine (JVM) software layer has been written to work with the
Jazelle hardware. The Java byte code acceleration is accomplished by the
following:
Hardware, which directly executes 80% of simple Java byte codes.
Function Data ARM instruction
Read context ID Context ID MRC p15,0,Rd,c13,c0,1
Write context ID Context ID MCR p15,0,Rd,c13,c0,1
31 0
Context identifier