Dynamic memory read configuration register, Register – Digi NS9215 User Manual
Page 237
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M E M O R Y C O N T R O L L E R
Dynamic Memory Read Configuration register
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237
The Dynamic Memory Refresh Timer register configures dynamic memory operation.
It is recommended that this register be modified during system initialization, or
when there are no current or outstanding transactions. Wait until the memory
controller is idle, then enter low-power or disabled mode.These bits can, however,
be changed during normal operation if necessary.
Note:
The Dynamic Memory Refresh Timer register is used for all four dynamic
memory chip selects. The worst case value for all chip selects must be
programmed.
Register
Register bit
assignment
Note:
The refresh cycles are evenly distributed. There might be slight variations,
however, when the auto-refresh command is issued, depending on the status
of the memory controller.
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D y n a m i c M e m o r y R e a d C o n f i g u r a t i o n r e g i s t e r
Address: A070 0028
The Dynamic Memory Read Configuration register allows you to configure the
dynamic memory read strategy. Modify this register only during system
initialization.
Note:
The Dynamic Memory Read Configuration register is used for all four dynamic
memory chip selects. The worst case value for all chip selects must be
programmed.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
REFRESH
Reserved
Bits
Access
Mnemonic
Description
D31:11
N/A
Reserved
N/A (do not modify)
D10:00
R/W
REFRESH
Refresh timer
0x0
Refresh disabled (reset value on
reset_n
)
0x1–0x77F n(x16)
16n
clk_out
ticks between SDRAM refresh cycles