Digi NS9215 - Manual (Page 77)

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I / O C O N T R O L M O D U L E
Memory Bus Configuration register
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Bit(s) Access Mnemonic Reset Description
D02:00 R/W CS0 0x4 Controls which system memory chip select is
routed to CS0
000
dy_cs_0
001 dy_cs_1
010 dy_cs_2
011 dy_cs_3
100 st_cs_0 (default)
101 st_cs_1
110 st_cs_2
111 st_cs_3
D05:03 R/W CS1 0x0 Controls which system memory chip select is
routed to CS1
000
dy_cs_0 (default)
001 dy_cs_1
010 dy_cs_2
011 dy_cs_3
100 st_cs_0
101 st_cs_1
110 st_cs_2
111 st_cs_3
D08:06 R/W CS2 0x5 Controls which system memory chip select is
routed to CS2
000
dy_cs_0
001 dy_cs_1
010 dy_cs_2
011 dy_cs_3
100 st_cs_0
101 st_cs_1 (default)
110 st_cs_2
111 st_cs_3
D11:09 R/W CS3 0x1 Controls which system memory chip select is
routed to CS3
000
dy_cs_0
001 dy_cs_1 (default)
010 dy_cs_2
011 dy_cs_3
100 st_cs_0
101 st_cs_1
110 st_cs_2
111 st_cs_3