Digi NS9215 - Manual (Page 216)

M E M O R Y C O N T R O L L E R
Static memory write control
216 Hardware Reference NS9215
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S t a t i c m e m o r y w r i t e c o n t r o l
Write enable
programming
delay
The delay between the assertion of the chip select and the write enable is
programmable from 1 to 16 cycles using the
WAITWEN bits of the Static Memory
Write Enable Delay (StaticWaitWen[3:0]) registers. The delay reduces the power
consumption for memories. The write enable is asserted on the rising edge of
HCLK
after the assertion of the chip select for zero wait states. The write enable is
always deasserted a cycle before the chip select, at the end of the transfer.
datamask_n (byte lane signal) has the same timing as st_we_n (write enable signal) for
writes to 8-bit devices that use the byte lane selects instead of the write enables.
SRAM
Write timing for SRAM starts with assertion of the appropriate memory bank chip
selects (
cs[n]_n ) and address signals ( addr[27:0]_n ). The write access time is determined
by the number of wait states programmed for the WAITWR field in the Static
Memory Write Delay register (see “Static Memory Write Delay 0–3 registers” on
page 257). The
WAITTURN field in the bank control register (see “StaticMemory Turn
Round Delay 0–3 registers” on page 258) determines the number of bus turnaround
wait states added between external read and write transfers.
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S t a t i c m e m o r y W r i t e : T i m i n g a n d p a r a m e t e r s
This section shows static memory write timing diagrams and parameters.
External memory
write transfer
with zero wait
states
This diagram shows a single external memory write transfer with minimum zero
wait states (
WAITWR=0 ). One wait state is added.
data
cs[n]
clk_out
addr
st_we_n
A
D(A)