Digi NS9215 - Manual (Page 508)

T I M I N G
Memory Timing
508 Hardware Reference NS9215
SPI slave mode 0
and 1: 2-byte
transfer
Note: SPI data can be reversed such that LSB is first. Use the BITORDER bit in Serial Channel
B/A/C/D Control Register A.
SPI slave mode 2
and 3: 2-byte
transfer
Note: SPI data can be reversed such that LSB is first. Use the BITORDER bit in Serial Channel
B/A/C/D Control Register A.
MSB LSB MSB LSB
MSB LSB MSB LSB
SP6 SP4
SP8 SP7
S10 SP5 SP1
S9 SP12 SP12 SP13 SP13 SP3 SP0
SPI CLK Out (Mode 0)
SPI CLK Out (Mode 1)
SPI Enable
SPI Data Out
SPI Data In
MSB LSB MSB LSB
MSB LSB MSB LSB
SP6 SP4
SP8 SP7
S10 SP5 SP1
S9 SP3 SP0
SPI CLK Out (Mode 2)
SPI CLK Out (Mode 3)
SPI Enable
SPI Data Out
SPI Data In