Digi NS9215 - Manual (Page 108)

W O R K I N G W I T H T H E C P U
MemoryManagement Unit (MMU)
108 Hardware Reference NS9215
The MMU table-walking hardware adds entries to the TLB. The translation
information that comprises both the address translation data and the access
permission data resides in a translation table located in physical memory. The MMU
provides the logic for automatically traversing this translation table and loading
entries into the TLB.
The number of stages in the hardware table walking and permission checking
process is one or two. depending on whether the address is marked as a section-
mapped access or a page-mapped access.
There are three sizes of page-mapped accesses and one size of section-mapped
access. Page-mapped accesses are for large pages, small pages, and tiny pages.
The translation process always begins in the same way — with a level-one fetch. A
section-mapped access requires only a level-one fetch, but a page-mapped access
requires an additional level-two fetch.
Translation table
base
The hardware translation process is initiated when the TLB does not contain a
translation for the requested MVA. R2: Translation Table Base (TTB) register points
to the base address of a table in physical memory that contains section or page
descriptors, or both. The 14 low-order bits [13:0] of the TTB register are
UNPREDICTABLE on a read, and the table must reside on a 16 KB boundary.
TTB register
format
The translation table has up to 4096 x 32-bit entries, each describing 1 MB of virtual
memory. This allows up to 4 GB of virtual memory to be addressed.
31 0 14 13
Translation table base