Digi NS9215 - Manual (Page 9)

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www.digiembedded.com 9
MMU faults and CPU aborts................................................................. 119
Alignment fault checking ............................................................ 119
Fault Address and Fault Status registers .......................................... 119
Priority encoding table............................................................... 120
Fault Address register (FAR)......................................................... 120
FAR values for multi-word transfers ............................................... 120
Compatibility issues .................................................................. 121
Domain access control ...................................................................... 121
Specifying access permissions....................................................... 121
Interpreting access permission bits ................................................ 121
Fault checking sequence.................................................................... 122
Alignment faults....................................................................... 123
Translation faults ..................................................................... 124
Domain faults .......................................................................... 124
Permission faults ...................................................................... 124
External aborts ............................................................................... 125
Enabling and disabling the MMU ........................................................... 125
Enabling the MMU ..................................................................... 125
Disabling the MMU .................................................................... 126
TLB structure ................................................................................. 126
Caches and write buffer .................................................................... 127
Cache features ........................................................................ 127
Write buffer............................................................................ 128
Enabling the caches .................................................................. 128
ICache I and M bit settings .......................................................... 129
ICache page table C bit settings.................................................... 129
R1 register C and M bits for DCache ............................................... 129
DCache page table C and B settings ............................................... 129
Cache MVA and Set/Way formats ......................................................... 130
Generic, virtually indexed, virtually addressed cache .......................... 131
ARM926EJ-S cache format ........................................................... 132
ARM926EJ-S cache associativity .................................................... 132
Set/way/word format for ARM926EJ-S caches ................................... 132
Noncachable instruction fetches .......................................................... 133
Self-modifying code .................................................................. 133
AHB behavior .......................................................................... 134
Instruction Memory Barrier .......................................................... 134
IMB operation .......................................................................... 134
Sample IMB sequences ............................................................... 135
C h a p t e r 4 : S y s t e m C o n t r o l M o d u l e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 7
Features ................................................................................ 137
Bus interconnection ......................................................................... 137
System bus arbiter........................................................................... 138