Digi NS9215 - Manual (Page 345)

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E X T E R N A L D M A
Static RAM chip select configuration
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DONE signal
The external peripheral can terminate the DMA transfer at any time by
asserting the DONE signal. The peripheral must also deassert the REQ signal
when it asserts the DONE signal.
The DONE signal can be asserted during a transfer but if the peripheral is
configured for burst access, the burst completes. When the DMA control logic
finds a DONE assertion, it closes the current buffer descriptor, asserts a
premature buffer completion status, and pauses until the REQ signal is
reasserted. The DONE cycle must be deasserted no later that four AHB clock
cycles before reasserting the REQ signal.
Special
circumstances
For memory-to-memory DMA transfers that are initiated by software writing a
1 to the channel go (CG) field in the DMA Control register, the DMA control
logic ignores the REQ and DONE signals.
For memory-to-peripheral transfers, the DMA control logic ignores the DONE
signal.
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S t a t i c R A M c h i p s e l e c t c o n f i g u r a t i o n
The AHB DMA controller accesses an external peripheral using the external memory
bus and one of the static ram chip select signals (
st_cs_n[N] ).
Static ram chip
select
configuration
This table shows how to program the static ram chip select control registers for
access using the AHB DMA controller. Fields not explicitly listed must be left in the
reset state. Fields listed but not defined must be defined by you.
Register name Field Value Comment
Configuration PB 1 System requirement
PM User-defined Set to 1 if it is not necessary for the chip
select signal to toggle for each access.
MW User-defined
Read Delay WTRD User-defined To determine the read delay:
1 Use this equation to compute the
total delay:
T
a
+ T
b
+ T
c
+ 10.0
7 Divide the total delay by the AHB clock
period
8 Round up any fractional value
Page Read Delay WTPG user-defined For most applications, this is the same value
as the WTRD value.