Interrupt status raw, Software watchdog configuration – Digi NS9215 User Manual
Page 178
S Y S T E M C O N T R O L M O D U L E
Interrupt Status Raw
178
Hardware Reference NS9215
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I n t e r r u p t S t a t u s R a w
Address: A090 016C
The Interrupt Status Raw register shows all current interrupt requests.
Register
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S o f t w a r e W a t c h d o g C o n f i g u r a t i o n
Address: A090 0174
The Software Watchdog Configuration register configures the software watchdog
timer operation.
Register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Interrupt status raw (ISRAW)
Interrupt status raw (ISRAW)
Bits
Access
Mnemonic
Reset
Description
D31:00
R
ISRAW
0x0
Interrupt status raw
Provides the status of all active, enabled, and
disabled interrupt request levels, where bit 0 is for
the interrupt assigned to level 0, bit 1 is for the
interrupt assigned to level 1, and so on through bit 31
for the interrupt assigned to level 31.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
SWTCS
De
bug
Re
serv
ed
SW
WIC
SW
WI
Re
serv
ed
SW
WE