Staticmemory turn round delay 0-3 registers, Staticmemory turn round delay 0–3 registers, Register register bit assignment – Digi NS9215 User Manual
Page 258
M E M O R Y C O N T R O L L E R
StaticMemory Turn Round Delay 0–3 registers
258
Hardware Reference NS9215
Register
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
S t a t i c M e m o r y T u r n R o u n d D e l a y 0 – 3 r e g i s t e r s
Address: A070 0218 / 0238 / 0258 / 0278
The Static Memory Turn Round Delay 0–3 registers allow you to program the number
of bus turnaround cycles. It is recommended that these registers be modified during
system initialization, or when there are no current or outstanding transactions. Wait
until the memory controller is idle, then enter low-power or disabled mode.
Register
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
WTWR
Bits
Access
Mnemonic
Description
D31:05
N/A
Reserved
N/A (do not modify)
D04:00
R/W
WTWR
Write wait states (WAITWR)
00000–11110
(n+2)
clk_out
cycle write access time. The wait
state time for write accesses after the first read is WAITWR
(n+2) x t
clk_out
11111
332
clk_out
cycle write access time (reset value on
reset_n
)
SRAM wait state time for write accesses after the first read.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
WTTN