Digi NS9215 - Manual (Page 341)

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E X T E R N A L D M A
Descriptor list processing
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Note:
Optimal performance is achieved when the destination address is aligned on a
word boundary.
Status
This field is not used. Read back 0x0000.
Wrap (W) bit
The Wrap (W) bit, when set, tells the DMA controller that this is the last buffer
descriptor within the continuous list of descriptors. The next buffer descriptor is
found using the initial DMA channel buffer descriptor pointer. When the W bit is not
set, the next buffer descriptor is found using an offset of 0x10 from the current
buffer descriptor.
Interrupt (I) bit
The Interrupt (I) bit, when set, tells the DMA controller to issue an interrupt to the
CPU when the buffer is closed due to a normal channel completion. The interruption
occurs regardless of the normal completion interrupt enable configuration for the
DMA channel.
Last (L) bit
The Last (L) bit, when set, tells the DMA controller that this buffer descriptor is the
last descriptor that completes an entire message frame. The DMA controller uses this
bit to assert the normal channel completion status when the byte count reaches zero.
Full (F) bit
The Full (F) bit, when set, indicates that the buffer descriptor is valid and can be
processed by the DMA channel. The DMA channel clears this bit after completing the
transfer(s).
The DMA channel does not try a transfer with the F bit clear. The DMA channel
enters an idle state upon fetching a buffer descriptor with the F bit cleared.
Whenever the F bit is modified by the device driver, the device driver must also
write a 1 to the CE bit in the DMA Control register to activate the idle channel.
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D e s c r i p t o r l i s t p r o c e s s i n g
Once a DMA controller has completed the operation specified by the current buffer
descriptor, it clears the F bit and fetches the next buffer descriptor. A DMA channel
asserts the NRIP field (buffer not ready interrupt pending) in the DMA Status
register and returns to the idle state upon fetching a buffer descriptor with the F bit
in the incorrect state. A DMA channel always closes the current descriptor and
moves on to the next descriptor when a DMA transfer is terminated by the assertion
of the DONE signal.