Digi NS9215 - Manual (Page 21)

. . . . .
www.digiembedded.com 21
UART FIFO Control register................................................................. 409
UART Line Control register ................................................................. 409
UART Modem Control register ............................................................. 411
UART Line Status register .................................................................. 411
UART Modem Status register ............................................................... 412
C h a p t e r 1 1 : S e r i a l C o n t r o l M o d u l e : H D L C . . . . . . . . . . . . . . . . . . . . . . . . . 4 1 5
HDLC module structure .............................................................. 415
Receive and transmit operations .......................................................... 415
Receive operation..................................................................... 416
Transmit operation ................................................................... 416
Transmitter underflow ............................................................... 416
Clocking ....................................................................................... 416
Bits ............................................................................................. 416
Last byte bit pattern table .......................................................... 417
Data encoding ................................................................................ 417
Encoding examples ................................................................... 417
Digital phase-locked-loop (DPLL) operation: Encoding ................................ 418
Transitions ............................................................................. 418
DPLL-tracked bit cell boundaries................................................... 419
NRZ and NRZI data encoding ........................................................ 419
Biphase data encoding ............................................................... 419
DPLL operation: Adjustment ranges and output clocks ................................ 419
NRZ and NRZI encoding .............................................................. 420
Biphase-Level encoding .............................................................. 420
Biphase-Mark and Biphase-Space encoding ....................................... 421
IRDA-compliant encode .............................................................. 421
Normal mode operation..................................................................... 421
Example configuration ............................................................... 421
Wrapper and HDLC Control and Status registers ........................................ 422
Register address map................................................................. 422
Wrapper Configuration register............................................................ 422
Interrupt Enable register ................................................................... 424
Interrupt Status register .................................................................... 425
HDLC Data Register 1........................................................................ 427
HDLC Data Register 2........................................................................ 427
HDLC Data register 3 ........................................................................ 428
HDLC Control Register 1 .................................................................... 429
HDLC Control Register 2 .................................................................... 429
HDLC Clock Divider Low .................................................................... 430
HDLC Clock Divider High .................................................................... 431
C h a p t e r 1 2 : S e r i a l C o n t r o l M o d u l e : S P I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 3
Features ................................................................................ 433