Gen id register, Registers register bit assignment – Digi NS9215 User Manual
Page 198
S Y S T E M C O N T R O L M O D U L E
Gen ID register
198
Hardware Reference NS9215
Registers
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
G e n I D r e g i s t e r
Address: A090 0210
This register is read-only, and indicates the state of addr[19:09] pins at powerup.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Chip select 3 base (CS3B)
Reserved
Chip select 3 base (CS3B)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Chip select 3 mask (CS3M)
Reserved
Chip select 3 mask (CS3M)
CSD3
Bits
Access
Mnemonic
Reset
Description
D31:12
R/W
CS3B
0x70000
Chip select 3 base
Base address for chip select 3.
D11:00
N/A
Reserved
N/A
N/A
D31:12
R/W
CS3M
0xF0000
Chip select 3 mask
Mask or size for chip select 3.
D11:01
N/A
Reserved
N/A
N/A
D00
R/W
CSD3
0x1
Chip select 3 disable
0
Disable chip select
1
Enable chip select