Registers register bit assignment – Digi NS9215 User Manual
Page 191
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S Y S T E M C O N T R O L M O D U L E
System Memory Chip Select 1 Dynamic Memory Base and Mask registers
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191
These control registers set the base and mask for system memory chip select 0, with
a minimum size of 4K. The powerup default settings produce a memory range of
0x0000 0000 — 0x0FFF FFFF
.
Registers
Register bit
assignment
S y s t e m M e m o r y C h i p S e l e c t 1 D y n a m i c M e m o r y B a s e a n d
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M a s k r e g i s t e r s
Addresses: A090 01D8 / 01DC
These control registers set the base and mask for system memory chip select 1, with
a minimum size of 4K. The powerup default settings produce a memory range of
0x1000 0000 — 0x1FFF FFFF
.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Chip select 0 base (CS0B)
Reserved
Chip select 0 base (CS0B)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Chip select 0 mask (CS0M)
Reserved
Chip select 0 mask (CS0M)
CSD0
Bits
Access
Mnemonic
Reset
Description
D31:12
R/W
CS0B
0x00000
Chip select 0 base
Base address for chip select 0
D11:00
N/A
Reserved
N/A
N/A
D31:12
R/W
CS0M
0xF0000
Chip select 0 mask
Mask or size for chip select 0
D11:01
N/A
Reserved
N/A
N/A
D00
R/W
CSD0
0x1
Chip select 0 disable
0
Disable chip select
1
Enable chip select