Digi NS9215 - Manual (Page 203)

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Memory Controller
C H A P T E R 5
T
he Multiport Memory Controller is an AMBA-compliant system-on-chip (SoC)
peripheral that connects to the Advanced High-performance Bus (AHB). The
remainder of this chapter refers to this controller as the memory controller.
Features
The memory controller provides these features:
AMBA 32-bit AHB compliancy
Dynamic memory interface support including SDRAM and JEDEC low-power
SDRAM
Asynchronous static memory device support including RAM, ROM, and Flash,
with and without asynchronous page mode
Can operate with cached processors with copyback caches
Can operate with uncached processors
Low transaction latency
Read and write buffers to reduce latency and improve performance,
particularly for uncached processors.
8-bit, 16-bit, and 32-bit wide static memory support.
16-bit and 32-bit wide chip select SDRAM memory support.
Static memory features, such as:
–
Asynchronous page mode read
– Programmable wait states
– Bus turnaround delay
– Output enable and write enable delays
– Extended wait