Dynamic memory control register, Register register bit assignment – Digi NS9215 User Manual
Page 235
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M E M O R Y C O N T R O L L E R
Dynamic Memory Control register
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235
Register
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D y n a m i c M e m o r y C o n t r o l r e g i s t e r
Address: A070 0020
The Dynamic Memory Control register controls dynamic memory operation. The
control bits can be changed during normal operation.
Register
END
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
Bits
Access
Mnemonic
Description
D31:01
N/A
Reserved
N/A (do not modify)
D00
R/W
END
Endian mode
0
Little endian mode
1
Big endian mode
The value of the endian bit on power-on reset (
reset_n
) is
determined by the
gpio_a[3]
signal. This value can be overridden by
software.
Note:
The value of the
gpio_a[3]
signal is reflected in this field.
When programmed, this register reflects the last value
written into the register. You must flush all data in the
memory controller before switching between little endian
and big endian modes.
CE
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
SDRAMInit
Reserved
Rsvd
nRP
Reserved
SR
Not
used
Rsvd
Not
used
Not
used