Interrupt status active, Register register bit assignment – Digi NS9215 User Manual
Page 177
. . . . .
S Y S T E M C O N T R O L M O D U L E
Interrupt Status Active
www.digiembedded.com
177
Register
Register bit
assignment
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I n t e r r u p t S t a t u s A c t i v e
Address: A090 0168
The Interrupt Status Active register shows the current active interrupt request.
Register
Register bit
assignment
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Interrupt service routine address (ISRA)
Interrupt service routine address (ISRA)
Bits
Access
Mnemonic
Reset
Description
D31:00
R/W
IS addr
0x0
Interrupt service routine address
A read to this register updates the priority logic
block and masks the current and any lower
priority interrupt requests.
Write the value of the interrupt level (0–31) to
clear the current priority level.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Interrupt status active (ISA)
Interrupt status active (ISA)
Bits
Access
Mnemonic
Reset
Description
D31:00
R
ISA
0x0
Interrupt status active
Provides the status of all active, enabled interrupt
request levels, where bit 0 is for the interrupt
assigned to level 0, bit 1 is for the interrupt assigned
to level 1, and so on through bit 31 for the interrupt
assigned to level 31.