Digi NS9215 - Manual (Page 210)

M E M O R Y C O N T R O L L E R
Static memory read control
210 Hardware Reference NS9215
“Static Memory Extended Wait register” on page 247 (StaticExtendedWait)
The number of cycles in which an AMBA transfer completes is controlled by two
additional factors:
Access width
External memory width
Programmable
enable
Each bank of the memory controller has a programmable enable for the extended
wait (EW). The WAITRD wait state field in the Static Memory Read Delay register can
be programmed to select from 1–32 wait states for read memory accesses to SRAM
and ROM, or the initial read access to page mode devices. The WAITWR wait state
field in the Static Memory Write Delay register can be programmed to select from 1–
32 wait states for access to SRAM. The Static Memory Page Mode Read Delay register
can be programmed to select from 1–32 wait states for page mode accesses.
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S t a t i c m e m o r y r e a d c o n t r o l
There are three types of static memory read controls:
Output enable programmable delay
ROM, SRAM, and flash
Asynchronous page mode read
Output enable
programmable
delay
The delay between the assertion of the chip select and the output enable is
programmable from 0 to 15 cycles using the wait output enable bits (WAITOEN) in
the Static Memory Output Enable Delay registers. The delay is used to reduce power
consumption for memories that cannot provide valid output data immediately after
the chip select has been asserted. The output enable is always deasserted at the
same time as the chip select, at the end of the transfer.
ROM, SRAM, and
Flash
The memory controller uses the same read timing control for ROM, SRAM, and flash
devices. Each read starts with the assertion of the appropriate memory bank chip
select signals (
cs_n ) and memory address ( addr[27:0] ). The read access time is
determined by the number of wait states programmed for the WAITRD field in the
Static Memory Read Delay register. The WAITTURN field in the Static Memory Turn
Round Delay register determines the number of bus turnaround wait states added
between external read and write transfers.