Digi NS9215 - Manual (Page 154)

S Y S T E M C O N T R O L M O D U L E
System configuration registers
154 Hardware Reference NS9215
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S y s t e m c o n f i g u r a t i o n r e g i s t e r s
All configuration registers must be accessed as 32-bit words and as single accesses
only. Bursting is not allowed.
Register address
map
Offset [31:24] [23:16] [15:8] [7:0]
A090 0000 General Arbiter Control
A090 0004 BRC0
A090 0008 BRC1
A090 000C BRC2
A090 0010 BRC3
A090 0014 Reserved
A090 0018 AHB Error Detect Status 1
A090 001C AHB Error Detect Status 2
A090 0020 AHB Error Monitoring Configuration
A090 0024 Timer Master Control
A090 0028 Timer 0 Reload Count and Compare register
A090 002C Timer 1 Reload Count and Compare register
A090 0030 Timer 2 Reload Count and Compare register
A090 0034 Timer 3 Reload Count and Compare register
A090 0038 Timer 4 Reload Count and Compare register
A090 003C Timer 5 Reload Count and Compare register
A090 0040 Timer 6 Reload Count and Compare register
A090 0044 Timer 7 Reload Count and Compare register
A090 0048 Timer 8 Reload Count and Compare register
A090 004C Timer 9 Reload Count and Compare register
A090 0050 Timer 0 Read and Capture register
A090 0054 Timer 1 Read and Capture register
A090 0058 Timer 2 Read and Capture register
A090 005C Timer 3 Read and Capture register
A090 0060 Timer 4 Read and Capture register
A090 0064 Timer 5 Read and Capture register
A090 0068 Timer 6 Read and Capture register
A090 006C Timer 7 Read and Capture register
A090 0070 Timer 8 Read and Capture register